Overview
communication between the MCU controller and external peripherals or another controller. Typical applications include external I/O or peripheral expansion with devices such as shift registers, display controllers, and analog-to-digital converters (ADCs). Communication between multiple devices is supported in SPI master or slave mode. The port supports 16-level receive and transmits FIFOs to reduce CPU load.
Components Required
- Launchxl-f28379d
- Logic annalyzer
- Jumper wires
Software:
- Code Composer Studio
- Circuit Diagram
Bill of Materials
Features
The SPI module features include:
- SPISOMI: SPI slave-output/master-input pin
- SPISIMO: SPI slave-input/master-output pin
- SPISTE: SPI slave transmit-enable pin
- SPICLK: SPI serial-clock pin
- Two operational modes: Master and Slave
- Baud rate: 125 different programmable rates. The maximum baud rate that can be employed is limited by the maximum speed of the I/O buffers used on the SPI pins. See the device-specific data manual for more details.
- Data word length: one to sixteen data bits
- Four clocking schemes (controlled by clock polarity and clock phase bits) include:
- – Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
- – Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
- – Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
- – Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
Simultaneous receive and transmit operation (transmit function can be disabled in software)
- Transmitter and receiver operations are accomplished through either interrupt-driven or polled
- algorithm
- 16-level transmit/receive FIFO
- DMA support
- High-speed mode
- Delayed transmit control
- 3-wire SPI mode
- SPISTE inversion for digital audio interface receive mode on devices with two SPI modules
Block Diagram
SPI Module Signals
GPIOs Required for High-Speed Mode
The high-speed mode of the SPI is available on the specified GPIO mux options in the device datasheet. To enable the high-speed enhancements, set SPICCR. HS_MODE to 1. Ensure that the capacitive loading on the pin does not exceed the value stated in the device Data Manual.
When not operating in high-speed mode, or if the capacitive loading on the pins exceeds the value stated in the device Data Manual, SPICCR. HS_MODE should be set to 0.
SPI Interrupts
This section includes information on the available interrupts present in the SPI module.
The SPI module contains two interrupt lines: SPIINT/SPIRXINT and SPITXINT. When the SPI is operating in non-FIFO mode, all available interrupts are routed together to generate the single SPIINT interrupt. When FIFO mode is used, both SPIRXINT and SPITXINT can be generated.
SPIINT/SPIRXINT
When the SPI is operating in non-FIFO mode, the interrupt generated is called SPIINT. If FIFO
enhancements are enabled, the interrupt is called SPIRXINT. These interrupts share the same interrupt vector in the Peripheral Interrupt Expansion (PIE) block.
In non-FIFO mode, two conditions can trigger an interrupt: a transmission is complete (INT_FLAG), or there is overrun in the receiver (OVERRUN_FLAG). Both of these conditions share the same interrupt vector: SPIINT.
The transmission complete flag (INT_FLAG) indicates that the SPI has completed sending or receiving the last bit and is ready to be serviced. At the same time, this bit is set, the received character is placed in the receiver buffer (SPIRXBUF). The INT_FLAG will generate an interrupt on the SPIINT vector if the SPIINTENA bit is set
The receiver overrun flag (OVERRUN_FLAG) indicates that a transmit or receive operation has been completed before the previous character has been read from the buffer. The OVERRUN_FLAG will generate an interrupt on the SPIINT vector if the OVERRUNINTENA bit is set and OVERRUN_FLAG was previously cleared.
In FIFO mode, the SPI can interrupt the CPU upon a match condition between the current receive FIFO status (RXFFST) and the receive FIFO interrupt level (RXFFIL). If RXFFST is greater than or equal to RXFFIL, the receive FIFO interrupt flag (RXFFINT) will be set. SPIRXINT will be triggered in the PIE block if RXFFINT is set and the receive FIFO interrupt is enabled (RXFFIENA = 1).
SPITXINT
The SPITXINT interrupt is not available when the SPI is operating in non-FIFO mode. In FIFO mode, the SPITXINT behaviour is similar to the SPIRXINT. SPITXINT is generated upon a match condition between the current transmit FIFO status (TXFFST) and the transmit FIFO interrupt level (TXFFIL). If TXFFST is less than or equal to TXFFIL, the transmit FIFO interrupt flag (TXFFINT) will be set. SPITXINT will be triggered in the PIE block
Data Format
The four-bit SPICHAR register field specifies the number of bits in the data character (1 to 16). This information directs the state control logic to count the number of bits received or transmitted to determine when a complete character has been processed.
The following statements apply to characters with fewer than 16 bits:
• Data must be left-justified when written to SPIDAT and SPITXBUF.
• Data read back from SPIRXBUF is right-justified.
• SPIRXBUF contains the most recently received character, right-justified, plus any bits that remain from previous transmission(s) that have been shifted to the left (shown in Example 18-1).
Transmission of Bit From SPIRXBUF
Conditions:
1. Transmission character length = 1 bit (specified in bits SPICHAR)
2. The current value of SPIDAT = 737Bh
Step by step code execution process
Step 1 GPIO Config
/////////////////////////////////////////////////////////////////////
void SPI_GPIO_Init()
{
EALLOW;
GPIO_setPinConfig(GPIO_58_SPISIMOA);
GPIO_setPinConfig(GPIO_59_SPISOMIA);
GPIO_setPinConfig(GPIO_60_SPICLKA);
GPIO_setPinConfig(GPIO_61_SPISTEA);
EDIS;
}
Step 2 SPI Init
void spi_init()
{
SPI_disableModule(SPIA_BASE);
SPI_setConfig(SPIA_BASE, DEVICE_LSPCLK_FREQ, SPI_PROT_POL0PHA1,
SPI_MODE_MASTER, 500000, 16);
SPI_disableFIFO(SPIA_BASE);
SPI_enableLoopback(SPIA_BASE);
SPI_setEmulationMode(SPIA_BASE, SPI_EMULATION_STOP_MIDWAY);
SPI_enableModule(SPIA_BASE);
}
Step 3 Transmit The Single Byte Data
void spi_TX(Uint16 a)
{
SpiaRegs.SPITXBUF = a;
}
Final code
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <math.h>
#include "F28x_Project.h"
#include "F2837xD_device.h"
#include "F2837xD_Examples.h"
#include "device.h"
#include "driverlib.h"
void SPI_GPIO_Init();
void spi_init();
void spi_TX(Uint16 a);
uint16_t sdata =1;
void main(void)
{
Device_init();
Device_initGPIO();
DINT;
SPI_GPIO_Init();
spi_init();
while(1)
{
spi_TX(sdata);
DEVICE_DELAY_US(100000);
sdata++;
}
}
void SPI_GPIO_Init()
{
EALLOW;
GPIO_setPinConfig(GPIO_58_SPISIMOA);
GPIO_setPinConfig(GPIO_59_SPISOMIA);
GPIO_setPinConfig(GPIO_60_SPICLKA);
GPIO_setPinConfig(GPIO_61_SPISTEA);
EDIS;
}
void spi_init()
{
SPI_disableModule(SPIA_BASE);
SPI_setConfig(SPIA_BASE, DEVICE_LSPCLK_FREQ, SPI_PROT_POL0PHA1,
SPI_MODE_MASTER, 500000, 16);
SPI_disableFIFO(SPIA_BASE);
SPI_enableLoopback(SPIA_BASE);
SPI_setEmulationMode(SPIA_BASE, SPI_EMULATION_STOP_MIDWAY);
SPI_enableModule(SPIA_BASE);
}
void spi_TX(Uint16 a)
{
SpiaRegs.SPITXBUF = a;
}
Output Waveforms
